In future large digital systems, synchronizing a whole chip with a single clock and neglible skew and jitter will be extremely difficult, if not impossible. Hence a single clock chip is relatively expensive. The problem of the global clock approach is that the distribution of the clock over the chip does not tolerate much delay variation since delay mismatch reduces the setup and hold time margins (slack) for longest and shortest paths respectively. A negative slack leads to malfunction of the IC (Integrated Circuit). Delay mismatch in the clock distribution network is called skew if it is caused by design, and jitter if it is caused by on-chip noise. In future process technologies, the delay mismatch must scale down since the delay of gates and flip-flops becomes smaller.
The delay of wires does not scale as transistors do. Hence the delay over long wires on a large IC will not fit any more in a single clock cycle which complicates reaching timing-closure in a design furthermore.
For these reasons, already todays large ICs are partitioned into several clock-domains where each clock-domain spans only a part of the chip area. In a clock domain, all signals are synchronized with the same clock signal. A signal in a clock domain may change only in response to an event on the clock signal, and all of the signals in a clock domain are stable during an aperture time associated with each clock event. Grouping signals into clock domains is advantageous since it allows these signals to be combined using logic circuits and sampled into clock storage elements without further synchronization. Membership in the clock domain is closed under simple composition rules. As long as two signals are in the same clock domain, logical combinations of the signals which do not exceed maximum or minimum delay constrains are in the clock domain. Also, it is always safe (i.e. no probability of synchronization failure) to sample a signal in the clock domain with a clocked storage element driven by the clock signal, and the result of this sampling is also in the clock domain.
However, communication between two clock-domains is not trivial since the frequency and phase relationship of the two clocks is in general nondeterministic. Therefore, inter clock-domain communication requires explicit synchronization, wherein signals from one clock domain must be synchronized to the local clock before they can be used in a different clock domain.
U.S. Pat. No. 5,450,458 A discloses a method and an apparatus wherein data transfer between subsystems of an information handling system employing a multiple subsystem clock environment architecture, or between multiple information handling systems operating with different clock frequencies, is synchronized using a timing aligned multiple frequency synthesizer with a synchronization window decoder. A frequency generation circuit in circuit communication with a data synchronization circuit functions to produce a synchronized timing signal(s) to permit a central processing unit operation in one subsystem clock environment to function with a peripheral subsystem(s), such as a memory controller, operating in a different subsystem clock environment, or permits information handling systems operating with different clock frequencies to function with one another. Data transfer synchronization delays are reduced and meantime-of-failure of signal synchronization accuracy is increased by eliminating metastability effects from the synchronization circuitry.
In U.S. Pat. No. 5,535,377 A, it is described a method and an apparatus for low latency synchronization of signals having different clock speeds. This method and apparatus are preferably used in systems where a first logic portion operating at a first clock speed, referred to as a fast clock speed, interfaces to a second logic portion operating at a second slower clock speed. A new slow clock is generated pseudo-synchronously from the fast clock using a phase locked loop (PLL) clock generator. The PLL multiplies the fast clock frequency up to the least common multiple (LCM) of the two frequencies to generate a base clock signal. The base clock is then divided down to form the slow clock signal. The PLL performs its operations in such a way that all three clocks have a fixed phase relationship. The rising edges of the base clock, fast clock and slow clock line up at periodic points and are skewed at other periodic points. Fast to slow synchronization logic and slow to fast synchronization logic are included which synchronize signals travelling between the logic portions. In the general case for a first logic portion having a fast clock frequency m and a second logic portion having a slow clock frequency n, the base clock frequency would be the LCM (m, n). The multiplexer in the slow to fast signal synchronization logic used to synchronize slow signals, i.e., signals from the second logic portion, to the faster clock frequency would have baseclock/m inputs. The multiplexor used to synchronize fast signals to the slower clock speed would have baseclock/n inputs.
U.S. Pat. No. 6,163,545 A describes a system for converting data in one clock-domain to a second clock-domain which system comprises a multiplexer having a select control which is synchronous with a first frequency and is coupled to two bistable registers of which a first is clock controlled in accordance with the first frequency and a second is clock controlled by the second frequency. The data output of the first register is looped back to the second data input of the multiplexer. The select signal operates to couple a data input to the first register whereupon the multiplexer then serves to couple the data output of the first register back to the data input thereof. The arrangement ensures availability of data at the first clock frequency beyond a transition of the second clock frequency. Thus data, preferably multi-bit address data, can be transferred from one clock-domain to another with less delay than in customary systems.
In the conventional systems, the incoming data is synchronized before the processing can start. However, this type of synchronization adds a significant amount of delay to the data communication and therefore increasing the latency.